1. Field of the Invention
The present invention relates to an AD conversion circuit and a solid-state image pickup device including this AD conversion circuit.
Priority is claimed on Japanese Patent Application No. 2012-173174, filed Aug. 3, 2012, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
As examples of a solid-state image pickup device using a TDC (=Time to Digital Converter) type AD conversion circuit, configurations described in Japanese Unexamined Patent Applications, First Publication Nos. 2008-92091 and 2009-38726 are known. FIG. 11 illustrates an extracted portion of a configuration of a TDC type AD conversion circuit when an oscillation circuit called a so-called “asymmetry type oscillation circuit” is used as a VCO (=Voltage Controlled Oscillator) of the AD conversion circuit. First, a configuration and an operation of the circuit of FIG. 11 will be described.
The circuit shown in FIG. 11 includes a VCO 1100, a latch unit 1108, a counting unit 1105, a detection circuit 1107, and an encoding circuit 1106. The VCO 1100 has an oscillation circuit in which 17 delay units (NAND circuits NAND[0] to NAND[16]) are connected in a ring form. The latch unit 1108 latches output signals (lower phase signals CK[0] to CK[16]) of the VCO 1100. The counting unit 1105 has a counter circuit that performs counting using the lower phase signal CK[15] from the NAND circuit NAND[15] output via the latch unit 1108 as a count clock. Further, the counting unit 1105 performs counting at a rising edge of the lower phase signal CK[15]. The detection circuit 1107 detects a predetermined logic state based on the lower phase signals CK[0] to CK[16] latched in the latch unit 1108. The encoding circuit 1106 encodes the logic state detected by the detection circuit 1107 into a binary number.
A start pulse StartP is input to one input terminal of the NAND circuit NAND0 constituting the VCO 1100, and an output signal of the NAND circuit NAND[16] is input to the other input terminal of the NAND circuit NAND0. A power supply voltage VDD is input to one input terminal of each of the NAND circuits NAND[1] to NAND[15], and an output signal of the NAND circuit of a preceding stage is input to the other input terminal. During an operation period of the AD conversion circuit, the power supply voltage VDD is set to a high level. An output signal of the NAND circuit NAND[13] is input to one input terminal of the NAND circuit NAND[16], and an output signal of the NAND circuit NAND[15] of a preceding stage is input to the other input terminal. The output signal of the NAND circuit NAND[13] is input to the NAND circuit NAND[16] after three stages, as well as the NAND circuit NAND[14] after one stage.
Next, an operation of the circuit shown in FIG. 11 will be described. FIG. 12 illustrates waveforms of the start pulse StartP and the output signals (the lower phase signals CK[0] to CK[16]) of the VCO 1100. First, as a logic state of the start pulse StartP changes from an L (Low) state to an H (High) state, the VCO 1100 starts a transition operation. In this transition operation, logic states of the signals output by the respective NAND circuits constituting the VCO 1100 change sequentially. The counting unit 105 starts counting and a reference signal generation unit (not shown) starts generation of a ramp wave (a reference signal) at the same time as the VCO 1100 starts the transition operation. The ramp wave generated by the reference signal generation unit is a signal whose level increases or decreases in one direction over time.
An analog signal as an AD conversion target and the ramp wave are input to a comparison unit (not shown). In parallel with this, the lower phase signals CK[0] to CK[16] are input to the latch unit 1108, and the lower phase signal CK[15] is input to the counting unit 105 via the latch unit 1108. When a magnitude relationship of the two input signals input to the comparison unit is changed, a comparison output CO of the comparison unit is inverted. At this time point, the latch unit 1108 latches logic states according to the lower phase signals CK[0] to CK[15], and the counting unit 105 latches a count value (an upper count value). The lower phase signals latched in the latch unit 1108 are encoded (binary-coded) as lower data of digital data by the detection circuit 1107 and the encoding circuit 1106, and the upper count value latched in the counting unit 1105 becomes upper data of the digital data. Accordingly, the digital data corresponding to the level of the analog signal can be obtained.
Hereinafter, the TDC type AD conversion circuit and the solid-state image pickup device using the same will be described. It is assumed that the signal (lower phase signals) held in the latch unit 1108 is a 16-bit data signal, and the count value (the upper count value) held in the counting unit 105 is an 8-bit data signal.
In encoding of the lower phase signals, it is preferable for multi-value comparison (detection as to whether a logic state of n (e.g., three) consecutive lower phase signals is a predetermined state) used for flash type ADC to be performed in time series while changing the lower phase signals of the comparison target. Specifically, a method of detecting that a logic state of three lower phase signals is a predetermined logic state, e.g., “001” (an L state, an L state and an H state) is performed in time series. This encoding method is applied to the TDC type AD conversion circuit using the asymmetry type oscillation circuit shown in FIG. 11.
For example, states of the lower phase signals CK[0] to CK[16] latched in the latch unit 1108 (combinations of respective logic states of the lower phase signals CK[0] to CK[16]) are all 16 states of state 0 to state 15, as shown in FIG. 12. When the counting unit 105 performs counting at a rising edge of the lower phase signal CK[15], the combinations of logic states of the lower phase signals CK[0] to CK[15] in each period obtained by dividing a period in which the counting unit 105 performs one counting (a period from the rising edge of the lower phase signal CK[15] to a next rising edge) in 16 are state 0 to state 15. State 0 to state 15 correspond to the encoding values 0 to 15 that are encoding results.
Hereinafter, content of a process of detecting that a logic state of three lower phase signals is a predetermined logic state (in this example, “001”) will be described. FIG. 13 illustrates waveforms of the start pulse StartP and the output signals (the lower phase signals CK[0] to CK[16]) of the VCO 1100. In FIG. 13, the lower phase signals CK[0] to CK[16] shown in FIG. 12 are arranged to be a group of signals rising (changing from an L state to an H state) sequentially at predetermined time intervals. Specifically, the respective lower phase signals are arranged in the order of the lower phase signals CK[0], CK[2], CK[4], CK[6], CK[8], CK[10], CK[12], CK[14], CK[1], CK[3], CK[5], CK[7], CK[9], CK[11], CK[13] and CK[15].
When a predetermined time (corresponding to a delay time for two NAND circuits) elapses after the lower phase signal CK[0] changes from an L state to an H state, the lower phase signal CK[2] changes from an L state to an H state, as shown in FIG. 13. When a predetermined time (corresponding to a delay time for two NAND circuits) elapses after the lower phase signal CK[2] changes from an L state to an H state, the lower phase signal CK[4] changes from an L state to an H state. Then, similarly, the lower phase signals CK[6], CK[8], CK[10], CK[12], CK[14], CK[1], CK[3], CK[5], CK[7], CK[9], CK[11], CK[13] and CK[15] sequentially change from an L state to an H state.
In encoding of the lower phase signals, logic states of three consecutive lower phase signals in the signal group (signal sequence) in which the lower phase signals CK[0], CK[2], CK[4], CK[6], CK[8], CK[10], CK[12], CK[14], CK[1], CK[3], CK[5], CK[7], CK[9], CK[11], CK[13] and CK[15] latched in the latch unit 1108 are arranged in this order are detected to sequentially enter an L state, an L state, and an H state, respectively, and the encoding value is determined according to a position in which the logic state is detected.
FIG. 14 illustrates a correspondence relationship between the logic state of the lower phase signals latched in the latch unit 1108 and the encoding value according to the logic state of the lower phase signals. In FIG. 14, the lower phase signals are arranged in the same order as the lower phase signals in FIG. 13. Specifically, the order when each lower phase signal in FIG. 13 is sequentially seen from top to bottom is the same as the order when each lower phase signal in FIG. 14 is sequentially seen from right to left.
In FIG. 14, “1,” “0” and “1/0” indicate logic states of the respective lower phase signals. “1,” “0” and “1/0” correspond to an “H state,” an “L state” and an “H state or L state,” respectively. The logic states of the lower phase signals input to the latch unit 1108 change in time series, and the encoding value according to a timing at which the lower phase signals are latched in the latch unit 1108 may be obtained.
In FIG. 14, the encoding value is determined to correspond to a signal combination in which logic states of three consecutive signals are sequentially “0,” “0” and “1.” For example, when the logic states of the lower phase signals CK[2], CK[0] and CK[15] are “0,” “0” and “1,” respectively, the encoding value is “0,” and when the logic states of the lower phase signals CK[4], CK[2] and CK[0] are “0,” “0” and “1,” respectively, the encoding value is “1.” Similarly, when the logic states of the lower phase signals CK[0], CK[15], and CK[13] are “0,” “0” and “1,” respectively, the encoding value is “15.”
However, logic states of three lower phase signals different from original ones may be detected to be “001” due to noise overlapping with the lower phase signals or the like, and a wrong encoding value may be obtained. For example, when the lower phase signals are latched in the latch unit 1108 at a timing at which a phase of the lower phase signal CK[0] advances relative to a phase of the lower phase signal CK[15] as shown in FIG. 15, the logic states of the lower phase signals latched in the latch unit 1108 are as shown in FIG. 16.
In this case, since the logic states of the lower phase signals CK[4], CK[2] and CK[0] latched in the latch unit 1108 are “0,” “0” and “1,” respectively, the encoding value is “1.” However, originally, the logic state of the lower phase signal CK[0] should be “0,” the logic states of the lower phase signals CK[0], CK[15] and CK[13] should be “0,” “0” and “1,” respectively, and the encoding value should be “15.” In this case, an error of “14” that is a difference between “15” and “1” occurs in the lower data. In the TDC type AD conversion circuit to which the above encoding method has been applied and the solid-state image pickup device using the same, an error greatly exceeding “1” is likely to occur in the lower data.